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DATA SHEET
MOS INTEGRATED CIRCUIT
PD4701A
INCREMENTAL ENCODER COUNTER
DESCRIPTION
The PD4701A is a counter for an X, Y 2-axis incremental encoder. When a two-phase encoder signal is input for the X and Y axes, direction discrimination and computation is performed, and count data is output in 8-bit parallel form. In addition, a 3-contact-point input buffer is incorporated, which is useful for applications which use a pointing device such as a mouse or track-ball. The CPU checks the switch input flag or count flag and reads the 12-bit count data in two operations, one for the lower byte and one for the upper byte. The key input flag is output together with the count data in the upper byte.
FEATURES
* X, Y 2-axis incremental encoder counter * Counter input (Schmitt-triggered input) X axis: XA, XB 2-phase signal 4-multiplication count method used Y axis: YA, YB 2-phase signal * Counters: 12-bit binary up/down counters (2 sets, X & Y) Reset value: 000H * Count data output: 8-bit parallel latch output x 2 (including key input flag) * On-chip 3-contact-point key input buffer circuit * CMOS * Single +5 V power supply
PIN CONFIGURATION (Top View) PIN NAMES
XA, YA : A-phase inputs XB, YB : B-phase inputs
XA XB RESET X YA YB RESET Y RIGHT LEFT 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD D7 D6 D5 D4 D3 D2 D1 D0 CS X/Y U/L
LEFT Key inputs MIDDLE
RIGHT CS X/Y U/L D0 to 7 CF SF : Chip Select : X/Y Counter Select : Upper/Lower Byte Select : Data outputs : Count flag : Count flag RESET X Counter RESET Y reset inputs
MIDDLE SF CF VSS
Document No. IC-3303 (1st edition) (O. D. No. IC-6947A) Date Published March 1997 P Printed in Japan
(c)
1993
PD4701A
ORDERING INFORMATION
Part Number Package 24-pin plastic DIP (600 mil) 24-pin plastic SOP (375 mil)
PD4701AC PD4701AGT
BLOCK DIAGRAM
XA XB
Phase Determination and Edge Detection
X-Axis Up/Down Counter
RESET X Data Multiplexer & Latch
CS X/Y U/L D0-7
RESET Y Count Flag Circuit Y-Axis Up/Down Counter
YA YB
Phase Determination and Edge Detection
CF
RIGHT LEFT MIDDLE Button Input Circuit
Switch Flag Circuit
SF
DATA MULTIPLEXER/LATCH BLOCK
X-Axis Counter
12-Bit Latch STB 8
X/Y U/L
Y-Axis Counter
12-Bit Latch STB
8
Data Multiplexer
8
3-State Buffer
D0 - 7
OE 4 4-Bit Latch STB CS To Count Flag Circuit
Button Input
2
PD4701A
PIN FUNCTIONS
Pin Name CPU interface block CS Input/Output Input Function Chip Select input. "L" input activates outputs D0 to 7. "H" input sets outputs D0 to 7 to high impedance. Output data is latched on the fall edge of CS. "L" must be maintained during a count data read. Counter Select input. "L" input selects the X counter, and "H" input selects the Y counter. Byte Select input. "L" input selects the lower byte and "H" input selects the upper byte, controlling data output. Counter reset inputs. RESET X input resets the X counter, and RESET Y input resets the Y counter. Both are active-"H". Bus for data output to the CPU. Outputs the byte data selected by the X/Y and U/L inputs. The data latched on the fall of CS is output. Counter flag output. Set (= "L" output) when the X or Y counter changes while CS = "H". Reset (= "H" output) on the fall of CS. While CS = "L", count flag output is disabled and the "H" level is output. Switch flag output. Becomes active (= "L" output) when the RIGHT, LEFT or MIDDLE switch input is "L". X counter 2-phase signal input pins
X/Y
Input
U/L
Input
RESET X RESET Y D0 to 7
Input
Output (3-state)
CF
Output
SF
Output
Mouse interface block
XA, XB
Input (Schmitt input) Input (Schmitt input) Input (Schmitt input)
YA, YB
Y counter 2-phase signal input pins
RIGHT LEFT MIDDLE
Key switch input pins. Key switch input are read as the high-order 4 bits of the X counter and Y counter upper byte as the internal status. Upper Byte SF L R M C11 C10 C9 C8
Key Input Status Power supply block VDD VSS +5 V power supply connection pin Ground pin
Count Data
3
PD4701A
DESCRIPTION OF OPERATIONS 1. COUNT OPERATION
The PD4701A executes an up-count and down-count by means of A & B 2-phase signals in the 12-bit up-down counter. An up-count is performed when the A-phase signals (XA, YA) are phase-advanced, and a down-count is performed when the B-phase signals (XB, YB) are phase-advanced. The edge of each signal is a count source. (4multiplication count method: see Fig. 1.) Fig. 1 Count Operation Timing Chart
Forward (Up-Count) Reverse (Down-Count)
(X, Y)A Input 1 2 3
Count Operation (X, Y)B Input
4
5
4
3
2
1
0
This count operation is executed independently for the X axis (XA, XB) and Y axis (YA, YB). This operation is initialized by reset input (RESET X, RESET Y) only. In an up-count, the next value after FFFH is 000H, and in a down-count, the next value after 000H is FFFH.
2. OPERATION OF COUNT FLAG, CF
The count flag, CF, indicates that a count source (either XA, B or YA, B edge input) has occurred while the CS signal is "H", and is an active-low output. CF is reset ( "H") by CS signal "L" input. While CS = "L", count flag output is disabled and the "H" level is output. Fig. 2 Count Flag Output Timing Chart
XA, B YA, B
CF
CS
Count Flag Output Disabled in these Periods
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PD4701A
3. SWITCH INPUT OPERATION
The PD4701A can process up to 3 contact points as switch inputs (active-"L" input). Switch input is read as part of the count data upper byte together with the switch flag status as an internal status (see Fig. 3). These are all active"H" outputs. The switch flag status, SF, is equivalent to the switch flag output, SF, described below. Fig. 3 Data Output Format
Bit No. Upper Byte 7 SF 6 L 5 R 4 M 3 C11 2 C10 1 C9 0 C8
Bit No. Lower Byte
7 C7
6 C6 SF : L: R: M: C11 - 0 :
5 C5
4 C4
3 C3
2 C2
1 C1
0 C0
Switch Flag Left Switch Right Switch Middle Switch Count Data (12 bit )
4. OPERATION OF SWITCH FLAG, SF
The switch flag, SF, becomes active (active-"L" output) when the RIGHT, LEFT or MIDDLE switch input is "L". SF can also be read as the switch flag status together with the count data.
5. DATA READ OPERATION
The CPU reads the count data and switch input status by controlling CS, X/Y and U/L. The relation between these is shown in Table 1. (At this time, the data latched on the falling edge of CS is output. If X/Y or U/L is switched while CS is still "L", the data at the point at which CS changes from "H" to "L" is read. When CS is set to "H", new data is read into the latch, and the new data is confirmed on the next fall of CS. Table 1 Data Output Table
CS 0 0 0 0 1 X/Y 0 0 1 1 x U/L 0 1 0 1 x D7
XC7
D6
XC6
D5
XC5
D4
XC4
D3
XC3 XC11 YC3 YC11
D2
XC2 XC10 YC2 YC10
D1
XC1 XC9 YC1 YC9
D0
XC0 XC8 YC0 YC8
SF
YC7
L
YC6
R
YC5
M
YC4
SF
L
R
M
FLOATING
5
PD4701A
6. CONNECTION TO CPU SYSTEM
An example of connection to a CPU system is shown in Fig. 4. Fig. 4 Example of Connection to CPU System
Output Port A2 - An and IORD or MRD A1 A0
RESET XY CS X/Y U/L YA YB D0 - 7 PD4701A RIGHT MIDDLE CF LEFT Mouse I/F XA XB
Mouse
CPU System
DB0 - 7
INT
FLAG
SF
PD4701A Pin Name
X/Y U/L CS
Description Connected to address line A1. Connected to address line A0. Connects address lines A2 to An and the signal resulting from decoding IORD in the I/O address mode or MRD in the memory address mode, or an output port. The low level must be maintained during a count data read. Connected to the data bus. When these are used as interrupt signals, they are connected to the CPU INT pin. These are connected to a CPU output port or reset signal.
D0 to 7 SF, CF RESET X RESET Y

The above connections enable the CPU to read the X counter, Y counter and switch input status.
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
6
PD4701A
An example of a PD4701A data read is shown in Fig. 5. Fig. 5 Example of PD4701A Data Read
Start
Count value latch
CS = 0
Count reset
RESET X = 1 RESET Y = 1
X counter low byte read
X/Y = 0 U/L = 0
X counter high byte & switch status read
X/Y = 0 U/L = 1
Y counter low byte read
X/Y = 1 U/L = 0
Y counter high byte & switch status read
X/Y = 1 U/L = 1
Data bus high impedance
CS = 1
End
* CS must be kept at "0" during the read.
7
PD4701A
7. APPLICATION AREAS
Two-phase incremental signals are used for detection and measurement of a vector quantity (a quantity that has direction and magnitude), and are widely employed in measuring instruments such as micrometers and linear scales, control systems for digital servo motors, X-Y tables, etc., head position control for printers, magnetic disks, etc., robot arm position control, and so on. The PD4701A incorporates the direction judgment circuit and count pulse generator required for 2-phase incremental signal processing, up/down counters for counting these pulses, and a data latch to hold the read data, in IC form, enabling an X, Y 2-axis incremental signal processing system to be implemented easily. In addition, a 3 switch-input buffer is incorporated, enabling this device to be widely used in man-machine interface and centronics interface application areas.
8. OPERATING PRECAUTIONS
1) As the PD4701A incorporates two sets of 12-bit counters, large transient currents flow during a count operation. Adecoupling capacitor of around 0.1 F should therefore be inserted between VDD and VSS of the PD4701A.
+5V VDD Tantalum electrolytic, laminated ceramic, or similar capacitor of around 0.1 F (Should be mounted right next to the IC.) VSS
PD4701A
2)
If a pulse shorter than the signal phase difference time tSAB (350 ns) is input to the A/B phase inputs (XA, XB, YA, YB) this will result in a miscount. Therefore, if pulses shorter than tSAB are to be input because of encoder bounds, etc., a filter should be attached to the A/B phase inputs.
PW
A or B Phase
B or A Phase
If PW tSAB (350 ns), the count value remains the same before and after pulse input. (UP count DOWN count or DOWN count UP count is implemented, and therefore the result is equivalent to no change in the count value.
8
PD4701A
ABSOLUTE MAXIMUM RATINGS (Ta = 25 C, VSS = 0 V)
PARAMETER Supply voltage Input voltage Output voltage Operating temperature Storage temperature Permissible loss SYMBOL VDD VI VO Topt Tstg PD RATING -0.5 to +7.0 -1.0 to VDD + 1.0 -0.5 to VDD + 0.5 -40 to +85 -65 to +150 500 UNIT V V V C C mW
DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = +5 V 10 %)
RATING MIN. Input voltage high Input voltage low VIL VIH 2.6 MAX. 0.8 V V XA, XB, YA, YB and LEFT, RIGHT, MIDDLE Other than the above IOL = 12 mA IOH = -4 mA VI = VDD, VSS VI = VDD, VSS
PARAMETER
SYMBOL
UNIT
TEST CONDITIONS
VIH Output voltage low Output voltage high Static consumption current Input current 3-state output leak current Dynamic consumption current Hysteresis voltage VOL VOH IDD II IOFF IDD dyn VH
2.2 0.45 VDD - 0.8 50 -1.0 -10 1.0 10 2 0.25
V V V
A A A
mA V
fIN = 500 kHz XA, XB, YA, YB and LEFT, RIGHT, MIDDLE
9
PD4701A
AC CHARACTERISTICS (Ta = -40 to +85 C, VDD = +5 V 10 %)
RATING MIN. XA, XB YA, YB Input cycle High-level pulse width Low-level pulse width Signal phase difference time R, L M SF High-level pulse width Low-level pulse width Setting delay time Reset delay time RESET W, Y Pulse width Count enable time Count clear time CF Flag setting time Flag reset time Count setting time CS CF enable time CF disable time Pulse width X/Y U/L D0 to 7 Address setup time Address hold time Output delay time Output delay time Floating time tCYAB tPWABH tPWABL tSAB tPWSWH tPWSWL tDSFL tDSFH tPWRS tSCTEN tDCTCL tDABCF tDCSCF tSCT tSCSCF tHABCS tPWCS tSACS tHCSAB tDCSD tDAD tFCSD 0 140 140 200 0 0 150 100 50 100 0 100 120 100 2 900 900 350 30 30 50 50 MAX.
PARAMETER
SYMBOL
UNIT
TEST CONDITIONS fin = 500 kHz
s
ns ns ns
s s
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Switch OFF Switch ON Switch ON Switch OFF
From RESETX, From RESETX, From XA,
B,
Y Y B

YA,
From CS From CF From CF From XA,
B,
YA,
B
To CS From CS From CS From X/Y, U/L From CS
AC TEST INPUT WAVEFORM
2.6 V 1.5 V 0.45 V Test Point 1.5 V
AC test : The input is driven by 2.6 V for logic "1", and 0.45 V for logic "0". Timing measurement is performed at 1.5 V for both logic "1" and logic "0".
10
PD4701A
Fig. 6 Two-Phase Signal & Switch Signal Input Timing
tCYAB
XA, YA XB, YB tSAB
tPWABH
tPWABL
tSAB
tSAB tPWSWL
tSAB tPWSWH
RIGHT LEFT MIDDLE
Fig. 7 Count Flag Output Timing
tPWRS
RESET X, Y
tSCTEN XA, B YA, B
tSAB
tDABCF
tDCSCF
CF tDCTCL tSCSCF tHABCS
CS tSCT tPWCS
11
PD4701A
Fig. 8 Data Output Timing
CS tSACS tHCSA
X/Y U/L tDCSD tDAD tFCSD
D0 - 7
Fig. 9 Switch Flag Signal Output Timing
RIGHT LEFT MIDDLE tDSFL tDSFH
SF
12
PD4701A
RECOMMENDED SOLDERING CONDITIONS
The following conditions (see table below) must be met when soldering this product. Please consult with our sales offices in case other soldering process is used, or in case soldering is done under different conditions.
TYPES OF SURFACE MOUNT DEVICE
PD4701AGT
Soldering process Infrared ray reflow Soldering conditions Peak package's surface temperature: 235 C or below, Reflow time: 30 seconds or below (210 C or higher), Number of reflow process: 2, Exposure limit*: None Peak package's surface temperature: 215 C or below, Reflow time: 40 seconds or below (200 C or higher), Number of reflow process: 2, Exposure limit*: None Solder temperature: 260 C or below, Flow time: 10 seconds or below, Number of flow process: 1, Exposure limit*: None Terminal temperature: 300 C or below, Flow time: 10 seconds or below, Exposure limit*: None Symbol IR35-00-2
VPS
VP15-00-2
Wave soldering
WS60-00-1
Partial heating method
* Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25 C and relative humidity at 65 % or less. Note Do not apply more than a single process at once, except for "Partial heating method". TYPE OF THROUGH HOLE MOUNT DEVICE
PD4701AC
Soldering process Wave soldering Soldering conditions Solder temperature: 260 C or below, Flow time: 10 seconds or below Symbol
13
PD4701A
24PIN PLASTIC DIP (600 mil)
24 13
1 A
12
K I L
J
H G
F D N
M
C B M R
NOTES 1) Each lead centerline is located within 0.25 mm (0.01 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM A B C D F G H I J K L M N R
MILLIMETERS 33.02 MAX. 2.54 MAX. 2.54 (T.P.) 0.500.10 1.2 MIN. 3.50.3 0.51 MIN. 4.31 MAX. 5.72 MAX. 15.24 (T.P.) 13.2 0.25 +0.10 -0.05 0.25 0~15
INCHES 1.300 MAX. 0.100 MAX. 0.100 (T.P.) 0.020 +0.004 -0.005 0.047 MIN. 0.1380.012 0.020 MIN. 0.170 MAX. 0.226 MAX. 0.600 (T.P.) 0.520 0.010 +0.004 -0.003 0.01 0~15 P24C-100-600-1
14
PD4701A
24 PIN PLASTIC SOP (375 mil)
24 13 detail of lead end
1 A
12 H I
G
3 +7 -3
J
F
E
K C D MM ITEM A B C D E F G H I J K L M N MILLIMETERS 15.71 MAX. 0.87 MAX. 1.27 (T.P.) 0.40+0.10 -0.05 0.125 0.075 2.9 MAX. 2.50 0.2 10.3 0.3 7.2 0.2 1.6 0.2 0.15+0.10 -0.05 0.8 0.2 0.12 0.10 B N P24GT-50-375B-1 INCHES 0.619 MAX. 0.035 MAX. 0.050 (T.P.) 0.016+0.004 -0.003 0.005 0.003 0.115 MAX. 0.098+0.009 -0.008 0.406+0.012 -0.013 0.283+0.009 -0.008 0.063 0.008 0.006+0.004 -0.002 0.031+0.009 -0.008 0.005 0.004 L NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
15
PD4701A
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5
2

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